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class-d audio power stage adau1513 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features integrated stereo power stage r ds-on < 0.3 (per transistor) efficiency > 90% short-circuit protection overtemperature protection applications flat panel televisions pc audio systems mini components general description the adau1513 is a 2-channel bridge-tied load (btl) class-d audio power stage. the power stage can drive the speaker loads of 4 at up to 15 w per channel at high efficiency. the 4-channel audio system can be formed when used with an adav4201 pulse-width modulator (pwm) processor using two adau1513s. the power stage accepts a 3.3 v logic differential pwm as input from an adav4201 processor. the power stage comprises thermal and output short-circuit protection with logic-level error flag outputs for interfacing to a system microcontroller along with reset and mute control of the power stage. the power stage operates from a range of power supply voltages from 9 v up to 18 v. the low power digital logic operates from a 3.3 v supply. the power stage can be used with modulators other than the adav4201. contact your local sales department for application assistance. functional block diagram a1 pvdd outl+ pgnd a2 b1 pvdd outl? pgnd b2 c1 pvdd outr+ pgnd c2 d1 pvdd outr? pgnd d2 level shift and dead time control temperature/ overcurrent protection mode control logic adau1513 voltage reference inl+ inl? inr+ inr? avdd agnd dvdd dgnd otw err mute stdn 06750-001 figure 1.
adau1513 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 performance summary................................................................ 3 power supplies .............................................................................. 3 digital i/o ..................................................................................... 4 pwm input logic table .............................................................. 4 digital timing............................................................................... 4 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function description .............................. 6 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 12 overview ..................................................................................... 12 power stage ................................................................................. 12 protection circuits ..................................................................... 12 thermal protection.................................................................... 12 overcurrent protection ............................................................. 12 undervoltage protection ........................................................... 12 automatic recovery from protections .................................... 12 mute and stdn ...................................................................... 13 power-up/power-down sequence .......................................... 13 applications information .............................................................. 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 5/07revision 0: initial version
adau1513 rev. 0 | page 3 of 16 specifications dvdd = 3.3 v, avdd = 3.3 v, pvdd = 15 v, ambient temperature = 25c, load impedance = 8 , me asurement bandwidth = 20 hz to 20 khz, unless otherwise noted. audio performance test data measured with adav4201. performance summary table 1. parameter min typ max unit test conditions/comments output power 1 1 khz 11 w 1% thd + n, 8 14 w 10% thd + n, 8 14.5 w 1% thd + n, 6 17.5 w 10% thd + n, 6 19 w 1% thd + n, 4 23 w 10% thd + n, 4 efficiency 90 % p out = 15 w r ds-on per high-side transistor 280 m i d = 100 ma per low-side transistor 250 m i d = 100 ma thermal characteristics thermal warning active 2 135 c die temperature thermal shutdown active 150 c die temperature overcurrent shutdown active 5 a peak total harmonic distortion plus noise (thd + n) 0.1 % p out = 1 w, 1 khz signal-to-noise ratio (snr) 96 db a-weighted, referred to 1% thd + n output dynamic range 96 db a-weighted, measured with ?60 dbfs input crosstalk between left and right channels 65 db @ 0 dbfs input 20 hz to 20 khz undervoltage trip threshold 5 v minimum output pulse width 50 ns 1 output powers above 15 w at 4 and above 18 w at 6 may need extra heat-sinking for continuous operation. 2 thermal warning flag is for indication of device t j reaching close to shutdown temperature. power supplies table 2. parameter min typ max unit test conditions/comments digital supply voltage (dvdd) 3.0 3.3 3.6 v analog supply voltage (avdd) 3.0 3.3 3.6 v power transistor supply voltage (pvdd) 9 15 18 v power-down current stdn held low avdd 2 3 a dvdd 50 55 a pvdd 55 600 a mute current mute held low avdd 0.5 0.6 ma dvdd 0.9 1.2 ma pvdd 0.3 0.9 ma operating current stdn and mute held high avdd 0.5 0.6 ma dvdd 1.1 2.5 ma pvdd 34 40 ma
adau1513 rev. 0 | page 4 of 16 digital i/o table 3. parameter min typ max unit test conditions/comments input voltage input voltage high 2.0 v input voltage low 0.8 v output voltage output voltage high 2.4 v @ 2 ma output voltage low 0.4 v @ 2 ma leakage current on digital inputs 10 a pwm input logic table table 4. mute inl+/inr+ inl ? /inr ? outl+/outr+ outl?/outr? mode low low/high low/high off off high-z high low low gnd gnd output damped high high low pvdd gnd positive output high low high gnd pvdd negative output high high high pvdd pvdd not used digital timing table 5. parameter min typ unit description t set 10 s wait time for unmute t hold 10 s wait time for shutdown t wait 100 ns wait time for applying input t pdl-h 13 ns propagation delay (low to high) t pdh-l 13 ns propagation delay (high to low) t outx +/outx? mute 600 ns time delay after mute held low until output stops switching 06750-002 outx+/outx? t pdh-l t pdl-h stdn mute inx+/inx? t set t wait figure 2. timing diagram unmute 0 6750-031 outx+/outx? t outx+/outx? mute stdn mute inx+/inx? t hold figure 3. timing diagram mute
adau1513 rev. 0 | page 5 of 16 absolute maximum ratings table 6. parameter rating dvdd to dgnd ?0.3 v to +3.6 v avdd to agnd ?0.3 v to +3.6 v pvdd to pgnd 1 ?0.3 v to +20.0 v pwm inputs dgnd ? 0.3 v to dvdd + 0.3 v mute / stdn inputs dgnd ? 0.3 v to dvdd + 0.3 v operating temperature range ?40c to +85c storage temperature range C65c to +150c maximum junction temperature 150c ja thermal resistance 26.7c/w jb thermal characterization (junction-board) 13.3c/w jt thermal characterization (junction-package top) 0.2c/w lead temperature soldering (10 sec) 260c vapor phase (60 sec) 215c infrared (15 sec) 220c 1 includes any induced voltage due to inductive load. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adau1513 rev. 0 | page 6 of 16 pin configuration and function description 06750-003 13 14 15 16 17 18 19 20 21 22 23 24 inr? inr+ mute stdn test4 test5 dgnd dvdd avdd agnd test6 test7 48 47 46 45 44 43 42 41 40 39 38 37 pgnd pgnd pvdd pvdd pvdd pvdd pvdd pvdd pvdd pvdd pgnd pgnd 1 2 3 4 5 6 7 8 9 10 11 12 outl? outl? outl? outl+ outl+ outl+ inl? inl+ otw test2 test3 outr? outr? outr+ outr+ outr+ test13 test12 test11 test10 test9 test8 35 outr? 36 34 33 32 31 30 29 28 27 26 25 adau1513 top view (not to scale) pin 1 indicator err notes 1. epad not shown and internally connected to pgnd, dgnd, and agnd for tqfp-48. 2. epad not shown and internally connected to pgnd and dgnd for lfcsp-48. figure 4. pin configuration table 7. pin function descriptions pin number mnemonic type 1 description 1, 2, 3 outl? o output of high power transistors, left channel negative polarity. 4, 5, 6 outl+ o output of high power transistors, left channel positive polarity. 7 inl? i differential pwm left input (?). 8 inl+ i differential pwm left input (+). 9 err o overtemperature shutdown error indicator (active low open-drain output). 10 otw o overtemperature warning indicator (active low open-drain output). 11 test2 i reserved for internal use. connect to dgnd. 12 test3 i reserved for internal use. connect to dvdd. 13 inr? i differential pwm right input (?). 14 inr+ i differential pwm right input (+). 15 mute i mute (active low input). 16 stdn i shutdown/reset input (active low input). 17 test4 i reserved for internal use. connect to dgnd. 18 test5 o reserved for internal use. do not connect. 19 dgnd p digital ground for digital circuitry. internally connected to exposed pad (epad) 2 . 20 dvdd p positive supply for digital circuitry. 21 avdd p positive supply for analog circuitry (can be tied to dvdd). 22 agnd p analog ground for analog circuitry. internally connected to epad 2 . can be tied to dgnd. 23 test6 i reserved for internal use. connect to dgnd. 24 test7 i reserved for internal use. connect to dgnd. 25 test8 i reserved for internal use. connect to dgnd. 26 test9 i reserved for internal use. connect to dgnd. 27 test10 i reserved for internal use. connect to dgnd. 28 test11 i reserved for internal use. connect to dgnd. 29 test12 i reserved for internal use. connect to dgnd. 30 test13 i reserved for internal use. connect to dgnd. 31, 32, 33 outr+ o output of high power transistors, right channel positive polarity.
adau1513 rev. 0 | page 7 of 16 pin number mnemonic type 1 description 34, 35, 36 outr? o output of high power tran sistors, right channel negative polarity. 37, 38, 47, 48 pgnd p power ground for high power transistors. internally connected to epad 2 . 39, 40, 41, 42, 43, 44, 45, 46 pvdd p positive power supply for high power transistors. 1 i = input, o = output, p = power. 2 epad is connected internally to pgnd, dgnd, and agnd.
adau1513 rev. 0 | page 8 of 16 typical performance characteristics 0 6750-004 output power (w) thd + n (db) ?80 ? 20 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 figure 5. thd + n vs. output power, 9 v, 4 06750-005 output power (w) thd + n (db) ?80 ? 20 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 figure 6. thd + n vs. output power, 9 v, 6 06750-006 output power (w) thd + n (db) ?80 ? 20 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 figure 7. thd + n vs. output power, 9 v, 8 0 6750-007 output power (w) thd + n (db) ?80 ? 20 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 figure 8. thd + n vs. output power, 12 v, 4 06750-008 output power (w) thd + n (db) ?80 ? 20 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 figure 9. thd + n vs. output power, 12 v, 6 0 6750-009 output power (w) thd + n (db) ?80 ? 20 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 figure 10. thd + n vs. output power, 12 v, 8
adau1513 rev. 0 | page 9 of 16 06750-010 output power (w) thd + n (db) ?80 ? 20 ?60 ?50 ?40 10m 10 100m 1 ?30 ?70 figure 11. thd + n vs. output power, 15 v, 4 0 6750-011 output power (w) thd + n (db) ?80 ? 20 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 figure 12. thd + n vs. output power, 15 v, 6 06750-012 output power (w) thd + n (db) ?80 ? 20 ?70 ?60 ?50 ?40 ?30 10m 10 100m 1 figure 13. thd + n vs. output power, 15 v, 8 06750-013 frequency (khz) output (dbr) ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 02 20 4 6 8 1012141618 0dbr = output power at 1% thd + n figure 14. fft, 1 w, 15 v, 8 06750-014 frequency (khz) output (dbr) ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 02 20 4 6 8 1012141618 0dbr = output power at 1% thd + n figure 15. fft, 60 dbfs, 15 v, 8 0 6750-015 frequency (khz) output (dbv) ?140 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?10 02 20 4 6 8 1012141618 ?20 0 20 10 ?130 figure 16. fft dither, 15 v, 8
adau1513 rev. 0 | page 10 of 16 06750-016 frequency (hz) thd + n (db) ?80 0 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 20 100 1k 10k figure 17. thd + n vs. frequency, 1 w, 15 v, 8 06750-017 frequency (hz) crosstalk (db) ?100 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 20 100 1k 10k left to right right to left figure 18. crosstalk, 0 dbfs, 15 v, 8 06750-018 t ambient (c) p diss max (w) 0 1 2 3 4 5 6 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 figure 19. power dissipation vs. ambient temperature 06750-019 output power (w) efficiency (%) 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 figure 20. efficiency vs .output power, 15 v, 4 0 6750-020 output power (w) efficiency (%) 0 5 10 15 20 25 0 10 20 30 40 50 60 70 80 100 90 figure 21. efficiency vs. output power, 15 v, 6 06750-021 output power (w) efficiency (%) 0 5 10 15 20 25 0 10 20 30 40 50 60 70 80 100 90 figure 22. efficiency vs. output power, 15 v, 8
adau1513 rev. 0 | page 11 of 16 06750-022 pvdd (v) output power (w) 0 30 25 5 10 15 20 61 8 89 71 01 2 11 1413 16 17 15 6 ? requires extra heat-sinking 4 ? 8 ? figure 23. output power vs. pvdd, 40 db thd + n 06750-023 pvdd (v) output power (w) 0 40 25 5 10 15 20 61 8 89 71 01 2 11 1413 16 17 15 6 ? 35 30 8 ? 4 ? figure 24. output power vs. pvdd, 20 db thd + n 06750-024 output power per channel, stereo mode (w) power dissipation (w) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 5 10 15 20 25 30 35 figure 25. power dissipation vs. output power, 4 0 6750-025 output power per channel, stereo mode (w) power dissipation (w) 0 1 2 3 4 5 6 0 5 10 15 20 25 figure 26. power dissipation vs. output power, 6 0 6750-026 output power per channel, stereo mode (w) power dissipation (w) 0 1 2 3 0 5 10 15 20 figure 27. power dissipation vs. output power, 8
adau1513 rev. 0 | page 12 of 16 theory of operation overview the adau1513 is a 2-channel integrated power stage designed to accept the logic level pwm inputs. the pwm inputs are amplified, low-pass filtered using a simple passive lc network, and then can be used to drive the speaker loads. the power stage has built-in circuits for overtemperature, overcurrent, short-circuit, and undervoltage protection. power stage the 2-channel adau1513 power stage comprises a total of eight half bridges. each half bridge is made up of pmos and nmos devices. the gate drive for the respective fets is generated internally and does not need a special gate drive supply or bootstrap capacitor compared to all nmos stages. this simplifies the high-side driver design and requires less external components. protection circuits the adau1513 includes comprehensive protection circuits. it includes thermal warning, thermal overheat, and overcurrent or short-circuit protection on the outputs. the err and otw outputs are open drain, requiring external pull-up resistors. the outputs are capable of sinking 10 ma. the open-drain outputs are useful in multichannel applications where more than one adau1513 are used. the error outputs of multiple adau1513s can be ored to simplify the system design. the logic outputs of the error flags ease the system design using a microcontroller. the power stage does not consist of protection in case pwm input stays high continuously. in such a case, the output pro- duces dc and it is possible to damage the speaker. to prevent this, ensure that the modulator is switching whenever the power stage is turned on. thermal protection thermal protection in the adau1513 is categorized into two error flags: one as thermal warning and the other as thermal shutdown. when the device junction temperature reaches near 135c (5c) the adau1513 outputs a thermal warning error flag by pulling otw (pin 10) low. this flag can be used by the microcontroller in the system as an indication to the user or can be used to lower the input level to the amplifier to prevent the thermal shutdown. the device continues operation until shutdown temperature is reached. when the device junction temperature exceeds 150c the device outputs an error flag by pulling the err (pin 9) low. this error flag is latched. to restore the operation, mute (pin 16) needs to be toggled to low and then to high again. overcurrent protection the overcurrent protection in the adau1513 is set internally at 5 a peak output current. the device protects the output devices against excessive output current by pulling the err (pin 9) low. this error flag is latched type. to restore the normal operation, mute (pin 16) needs to be toggled to low and then to high again. the error flag is useful for the microcontroller in the system to indicate an abnormal operation and to initiate the audio mute sequence. the device senses the short-circuit condition on the outputs after the lc filter. typical short-circuit conditions include shorting of the output load and shorting to either pvdd or gnd. undervoltage protection the adau1513 has an undervoltage protection circuit that senses the undervoltage on pvdd. when the pvdd supply goes below the operating threshold, the output fets are turned to a high-z condition. also, the device issues an error flag by pulling the err pin low. this condition is latched. to restore the operation, mute (pin 16) needs to be toggled to low and then to high again. automatic recovery from protections in certain applications, it is desired for the amplifier to recover itself from thermal protection without the need for system microcontroller intervention. the adau1513 thermal protection circuit issues two error signals for this purpose: one thermal warning ( otw ) and the other thermal shutdown ( err ). with these two error signals, there are two options for using the protections: ? option 1: using otw ? option 2: using err the following sections provide further details of these two options. option 1: using otw the otw pin is pulled low when the die temperature reaches 130c to 135c this pin can be wired to the mute pin using an rc circuit as shown in figure 28. 06750-027 a dau1513 otw to mute logic input d1 1n4148 dvdd r1 100k ? 10 15 mute c1 47f figure 28. option 1 schematic for autorecovery the low logic level on otw also pulls down the mute pin. the bridge is shut down and, therefore, starts cooling or the die temperature starts reducing. when it reaches 120c, the otw signal starts going high. while this pin is tied to a capacitor with a resistor pulled to dvdd, the voltage on this pin starts rising slowly towards dvdd. when it reaches the input logic high threshold, mute is deasserted and the
adau1513 rev. 0 | page 13 of 16 amplifier starts functioning again. this cycle repeats itself depending on the input signal conditions and the temperature of the die. this option allows part operation that is safely below the shutdown temperature of 150c and allows the amplifier to recover itself without the need for microcontroller intervention. option 2: using err option 2 is similar to option 1 if the err pin can be tied to mute instead of otw . see the circuit in figure 29. 06750-028 adau1513 err to mute logic input d1 1n4148 dvdd r1 100k ? mute c1 47f 9 15 figure 29. option 2 schematic for autorecovery in this case, the part goes into shutdown mode due to any of the error-generating events like output overcurrent, overtemperature, missing pvdd or dvdd, or clock loss. the part recovers itself based on the same circuit operation in figure 28. however, if the part goes into error mode due to overtempera- ture, then the device would have reached its maximum limit of 150c (15c to 20c higher than option 1). if it goes into error mode due to an overcurrent from a short circuit on the speaker outputs, then the part will keep itself recycling on and off until the short circuit is removed. it is possible that, with this operation, the part is subjected to a much higher temperature and current stress continuously. this, in turn, reduces the parts reliability in the long term. therefore, using option 1 for autorecovery from the thermal protection and using the system microcontroller to indicate to the user of an error condition is recommended. mute and stdn the mute and stdn are 3.3 v logic-compatible inputs used to control the turn-on/turn-off for adau1513. the stdn input is active low when the stdn pin is pulled low and the device is in its energy-saving mode. the power stage is in high-z state. the high logic level input on the stdn pin will wake up the device. the logic circuits are running internally but the power stage is still in high-z state. when the mute pin is pulled high, the power stage is active and starts responding to pwm inputs. the low level on the mute pin disables the power stage and is recommended to be used to mute the audio output. see the power-up/power-down sequence section for more details. power-up/power-down sequence figure 30 shows the recommended power-up sequence for the adau1513. 06750-029 avdd/dvdd pvdd stdn outx+/outx? inx+/inx? mute t set t pdl-h t wait figure 30. recommended power-up sequence the adau1513 does not have any pop-and-click suppression circuits; therefore, care must be taken during the power-up. the power stage stays in hi-z on power-up. however, it is recom- mended to ensure that stdn and mute are held low during initial power-up. first, stdn should be pulled high followed by mute to turn on the power stage. the power stage turns on after the mute signal is pulled high and responds to pwm inputs after a small propagation delay of 200 s. the special turn-on sequence may be necessary depending on the pwm used to prevent the turn-on pop or click. however, if the adav4201 processor is used, the processor has a built-in special turn-on pwm sequence. the processor sends a unique pwm input start sequence that ensures soft turn-on. if another modulator is used, care must be taken to ensure that the modulator has built-in pop-and-click suppression. also, because the power stage does not track the pwm inputs, it is recommended to use the system microcontroller to ensure that the modulator is ready to send the pwm sequence before turning on the power stage. similarly, for muting the amplifier, it may be necessary to supply a special muting pwm sequence for minimum pop and click. the adav4201 processor has a built-in feature that takes care of this need. if any other modulator is used, care must be taken during muting of the power stage. the system microcontroller can be used to handle the mute/unmute of the power stage as well as a modulator. the error outputs of the power stage should be connected to the microcontroller port. this error flag can be used to inform the modulator that the power stage is shut down and to mute the pwm inputs. on removal of the error condition, the microcontroller should initiate an unmute sequence to mini- mize pop and click while power stage is turning on/turning off. the adau1513 uses three separate supplies: avdd (3.3 v analog for internal reference), dvdd (3.3 v digital for control logic and clock oscillator), and pvdd (9 v to 18 v power stage and level shifter). separate pins are provided for the avdd,
adau1513 rev. 0 | page 14 of 16 dvdd, and pvdd supply connections, as well agnd, dgnd, and pgnd. in addition, the adau1513 incorporates a built-in undervoltage lockout logic on dvdd as well as pvdd. this helps detect undervoltage operation and eliminates the need to have an external mechanism to sense the supplies. the adau1513 monitors the dvdd and pvdd supply voltages and prevents the power stage from turning on if either of the supplies are not present or below the operating threshold. therefore, if dvdd is missing or below the operating thresh- old, for example, the power stage will not turn on, even if the pvdd is present or vice versa. because this protection is only present on dvdd and pvdd and not on avdd, shorting both avdd and dvdd externally or generating avdd and dvdd from one power source is recommended. this ensures both avdd and dvdd supplies are tracking each other and avoids the need to monitor the sequence with respect to pvdd. this also ensures minimal pop and click during power-up. when using separate avdd and dvdd supplies, ensure that both supplies are stable before unmuting or turning on the power stage. during power-up, it is recommended to keep stdn and mute low to ensure that the power stage stays in high-z mode. similarly, during shutdown, pulling mute to logic low before pulling stdn down is recommended. however, where a fault event occurs, the power stage will shut down to protect the part. in this case, depending on the signal level, there is some pop at the speaker. during shutdown of the power supplies to reduce power consumption, it is highly recommended to mute the amplifier first, followed by pulling stdn low before shutting down any of the supplies. after mute is pulled low, the power supplies can be shut down in the following order: pvdd, dvdd, then avdd. where avdd and dvdd are generated from a single source, ensure that pvdd is tuned off before dvdd and avdd, and after issuing mute and stdn .
adau1513 rev. 0 | page 15 of 16 applications information refer to the application schematic in figure 31 for details on connections and component values. for details on the pwm modulat or part, refer to the adav4201 data sheet. for applications with pvdd > 15 v, add components r1 and r2 = 10 typical, c5 and c6 = 680 pf typical, and d1 through d8 = crs 01/02. d4 d3 pvdd r1 10 ? l2 l1 d1 d2 pvdd adau1513 c1 c2 c5 680pf d7 d8 pvdd r2 10 ? l4 l3 d5 d6 pvdd c3 c4 c6 680pf 06750-030 dgnd pgnd dvdd avdd agnd pvdd pvdd 3.3v outl? outr? outl+ test4 otw test3 outr+ test9 test8 test13 test12 test11 test10 test7 test6 mute stdn err 470f 1f 100nf 100nf 100nf 100nf test2 system logic control or microcontroller inr? i 2 c control sda scl inl? inl+ inr+ pulse-width modulator adav4201 figure 31. application schematic table 8. suggested low-pass filter values load impedance () inductance l1 to l4 (h) capacitance c1 to c4 (f) 4 10 1.5 6 15 1 8 22 0.68
adau1513 rev. 0 | page 16 of 16 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 32. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters compliant to jedec standards ms-026-abc 0.50 bsc lead pitch 0.27 0.22 0.17 7.20 7.00 sq 6.80 37 37 48 48 1 13 12 1 12 24 13 24 25 36 25 36 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw 7 3.5 0 0.15 0.05 1.20 max top view (pins down) bottom view (pins up) 5.10 sq exposed pad 9.20 9.00 sq 8.80 s e a t i n g p l a n e 0 . 7 5 0 . 6 0 0 . 4 5 1 . 0 0 r e f 042507-a v i e w a pin 1 figure 33. 48-lead thin quad flat package, exposed pad [tqfp_ep] (sv-48-5) dimensions shown in millimeters ordering guide model temperature range package description package option adau1513acpz 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 adau1513acpz-rl 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq], 13 tape and reel cp-48-1 adau1513acpz-rl7 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq], 7 tape and reel cp-48-1 adau1513asvz 1 ?40c to +85c 48-lead thin quad flat package, exposed pad [tqfp _ep] sv-48-5 ADAU1513ASVZ-RL 1 ?40c to +85c 48-lead thin quad flat package, exposed pad [tqfp _ ep], 13 tape and reel sv-48-5 ADAU1513ASVZ-RL7 1 ?40c to +85c 48-lead thin quad flat package, exposed pad [tqfp _ ep], 7 tape and reel sv-48-5 1 z = rohs compliant part. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06750-0-5/07(0)

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